Orchid converts Bayer pixel data with Cyclone FPGA
Converting CMOS imager Bayer-pattern pixel data to RGB pixel data can be readily accomplished using low-cost FPGA technology devices.
Pixels within modern CMOS image sensors are typically arranged in a Bayer colour pattern.
Image data is scanned from left to right and from top to bottom.
Each scanned raw pixel is actually a monochrome colour element, either red, green or blue.
Inherent characteristics of the human eye make it advantageous to have twice as many green pixels as red or blue ones.
To render a CMOS imager's output human-viewable, a conversion from the Bayer image-data format to an RGB image-data format is necessary.
A common method of converting Bayer image data to RGB data is the bi-linear-interpolation method, in which a 3 x 3 Bayer-pixel matrix is mathematically combined into a single pixel with separate red, green and blue data-component values.
Thus a 3 x 3 matrix of monochrome pixels is transformed into a single pixel with three component values.
The mathematics for bi-linear interpolation (as well as algorithms for other image conversion methods) can be found in industry text books.
Orchid implemented the bi-linear interpolation based image-conversion using an Altera Cyclone III FPGA.
It selected the Cyclone III FPGA device for its low-cost resource-rich architecture.
It began its FPGA implementation by dividing the complex function up into seven individual building blocks.
These blocks were: Input Data Formatter, Image Line Data Memory, Image Line Data Selector, Bayer Matrix Calculator, Output Data Formatter, PLL Clocking and Control and Built In Test Pattern Generator.
It worked with Altera's Quartus II development platform to implement and test each subsystem.
Orchid's goal was the development of a 10bit-wide conversion system that preserved data-width throughout the process.
Preservation of colour depth and resolution was necessary for the application.
Many low-cost commercial imagers will provide RGB 565 data, YUV 4:2:2 data or some other truncated colour depth output.
Unique to its conversion approach was the 30bit-wide colour depth with 10bit per pixel per colour.
Its approach was designed for a maximum line width of 1024 pixels at a maximum input pixel rate of 27MHz.
Orchid's Cyclone III implementation required one PLL block, 462 logic cells, 219 logic registers, 81920 internal memory bits, and 40 IO pins.
Implemented in an EP3C5E144 device, its resource usage was less than 10 per cent for logic element utilisation and less than 20 per cent for memory bit utilisation.
Plenty of resources remain for the implementation of other complex system-features.
Its image processor was an easy fit for the Cyclone III device.
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