Meeting today's design challenges

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Edited by the Electronicstalk editorial team Dec 24, 2002

Phil Loughhead outlines the limitations of current design capture solutions when faced with the challenges presented by evolving component technologies and design demands.

Capturing an electronic circuit in the form of a schematic drawing has been the standard way of designing electronics for many years, and is still one of the most widely used electronics design formats today.

While electronics technology has moved ahead in leaps and bounds in the last decade, computer-based schematic capture tools have remained fairly static in their capabilities and feature sets.

For digital design, hardware description languages (HDLs) such as VHDL offer many advantages over traditional schematic capture, particularly in the design of programmable logic devices such as FPGAs.

However, the text-based nature of HDLs means that they do not have the capability to convey complex information visually, as schematics do.

The challenge for EDA software vendors is to combine the graphical power of schematic capture with the logic construction capabilities of HDLs, and present them within a single, integrated application.

nVisage, Altium's new multidimensional design capture tool, seeks to meet this challenge by offering engineers full schematic and VHDL design and development capabilities within a single application that is equally at home in the PCB or FPGA worlds.

An electronic design is a collection of connected components.

Essentially there are four types of components that can be used to implement an electronic design: predefined off-the-shelf components, such as discretes and standard ICs; programmable components, such as PLDs and FPGAs; program-executing components, such as MCUs, MPUs and DSPs; and custom designed ASICs.

The vast majority of designs use a combination of the first three types of components, the fourth type reserved for those designs that can afford the high nonrecoverable engineering development costs.

The engineer's ability to choose which of the three commonly accessible component types they will use to implement their design is not only driven by the requirements of their design, it is also influenced by their access to suitable capture and implementation tools, and their ability to design in the methodology required by that tool.

For example, the recent growth in capacity and reduction in price of FPGAs makes them an attractive choice for implementing large and complex digital systems - the benefits include reduced component count and design size, design reconfigurability, and design security, to name a few.

Before FPGAs can be considered a mainstream design option, however, a number of questions must be answered.

Are these FPGAs accessible as an implementation option for the engineer? Even if the engineer has the capture skills, are suitable capture tools affordable? Do they lock the engineer into a specific vendor's technology? Do they interface to the engineer's PCB implementation tools and company systems? The ideal capture system supports all implementation options, giving the engineer complete freedom on how they partition and implement their design.

The initial release of nVisage supports design for implementation using predefined and programmable components.

Design capture options have, to some extent, developed in response to the requirements of the implementation mode.

A schematic of interconnected logical symbols is an excellent way of representing the set of physical components interconnected on the PCB - each component's behaviour is defined by the component manufacturer, the engineer uses this behaviour to suit their design requirements.

The programmable architecture of an FPGA presents different demands.

Either the designer can capture their FPGA design using the simple low-level building blocks available in the FPGA, or by using a hardware description language, then synthesising it into the low-level blocks available in the target device.

HDLs, such as VHDL, offer the advantage of abstract, high-level design methodologies present in a structured programming language, which is ideal for describing large digital designs.

Schematic capture is a mature and proven approach to designing with off the shelf components.

FPGA design, however, has remained the domain of specialised point tools, vendor's device-specific tools, or high-cost workstation tools.

Why? Because a complete FPGA design solution is made up from a number of separate but equally important ingredients, which include: integrated, mixed schematic and VHDL capture; schematic primitive and macro libraries with support for VHDL models; VHDL simulation and debugging, with timing back annotation; VHDL synthesis with support for all major device vendors; and pin data back annotation from vendor place and route tools.

The complete capture solution is one which allows the designer to mix and match capture methods to suit their requirements; using low-level primitive and macro schematic components, writing VHDL to implement sections, or even creating their own schematic components to represent large logical elements in the design, then writing VHDL to implement the functionality of these created components.

nVisage's ability to mix multiple capture methods allows the designer to optimally apply the strengths of each capture mode within a single design.

The Design Explorer (DXP) software integration platform that nVisage is built on also allows for the future addition of editors, debuggers and compilers for MCU, MPU and DSP design.

Another challenge that many engineers face is repeated sections of circuitry within their design.

While older capture tools sometimes included features to handle this during initial capture, once the design was ready for transfer to implementation, the design had to be flattened - a process that simply copied and pasted the repeated sections of the design to logically instantiate every physical component.

When the design required updating the engineer was faced with the odious and error prone task of individually updating the repeated sections.

Full support for design instantiation without flattening the source hierarchy is a core behavioural feature of high-level programming languages such as VHDL, but has not previously been available in a schematic capture environment.

nVisage brings HDL reuse concepts to the schematic capture space, both in the specification of multiple instantiations and in the management of mapping from the single logical entity to its multiple physical entities.

True multi-channel schematic design is a substantial bonus for designs targeting PCB implementation - particularly when it is backed up by a PCB layout tool that supports step and repeat of placement and routing, such as Protel DXP.

True multichannel schematic design brings a state change to the schematic capture process and gives the engineer complete freedom in defining the mix of schematic and VHDL in their FPGA design.

Design validation is no longer a process of checking for human and logical errors introduced during design capture - the increasing complexity of designs coupled with potential signal quality and integrity issues requires that the engineer perform high-level engineering analysis and verification during the capture stage.

Not only is the design task more complex, today's competitive pressures demand that designs are tightly engineered to maximise the performance whilst minimising the cost, all the while meeting the time-to-market pressures.

Recent surveys show that while some 30% of engineers use simulation and signal analysis tools today, within 2 years approximately 60% predict they will need them.

Engineers no longer have the luxury of verifying their designs once they are implemented then taking a couple of iterations to debug them - they need to analyse, tune and verify the design as early as possible in the design cycle.

To do this they need access to the complete range of simulation and pre-layout signal integrity analysis tools during the capture stage.

Signal integrity issues can occur when device switching speeds approach the time it takes for the signal to propagate through the routed connection.

With the continual improvements in component fabrication technologies delivering approximately 30% faster switching speeds every 3 years, most digital engineers will need to take account of signal degradation, timing errors, crosstalk or electromagnetic interference problems at some point in their careers, even if they are not involved in designing circuits with high clock speeds.

An essential requirement to designing to avoid signal integrity issues is impedance matching - achieved through correct definition of the physical characteristics of the PCB materials and the routing, as well as correct device matching and termination.

nVisage's pre-layout signal integrity analysis puts this analysis in the right hands - the design engineer's.

Rather than discovering that the design requires termination components after PCB layout, the engineer can confirm component matching and add terminations prior to layout.

nVisage also includes Spice mixed-signal circuit simulation to tune and verify the schematic before PCB layout.

VHDL simulation allows the engineer to verify the FPGA prior to synthesis and place and route, and then back annotate the place and route timing information to confirm that it remains within spec.

Multiple analysis modes integrated into the design capture process are essential if the engineer is to satisfy the demand of "correct-by-design", and meet time-to-market requirements.

The basis of every engineering design is the components.

Not only do engineers need the components in a symbolic form on the schematic, they may also need to model the components for circuit simulation, analyse the components' impact on the signal integrity, or implement a large-scale logical component in VHDL and tie it to a schematic symbol for their FPGA designs.

This component modelling needs to be achieved without imposing unnecessary weight on the design process.

Ideally each model kind is only added by the designer when required.

The component is also the link from the engineering design environment into a company's inventory management system.

Engineers select components from the preferred parts, and then once the design is complete, they pass the design back into the company system in the form of a bill of materials (BOM).

To streamline this process, the design environment must support linking from the components to the company database during the capture process, and then output a BOM in a form that readily translates back into the company's system when the design is complete.

nVisage's integrated component libraries satisfy these multiple demands, supporting simple schematic-to-PCB components right through to fully modelled, database-linked, ready-to-manufacture component libraries.

Time to market and design complexity issues are not only solved at the design tool level, companies resolve them by building teams that bring together the right mix of expertise and parallel design effort to the project.

To do this effectively, each team member must have appropriate access to the correct set of design data without fear of impacting on the efforts of their colleagues.

There are mature and complete solutions available for access management and revision control of design data created in an electronic form; commonly referred to as version control software (VCS).

nVisage includes a standard interface to 3rd party version control software, such as Microsoft Visual SourceSafe.

Another growing requirement of a competitive electronic product development company is to extract the maximum return from their expensive research and development investments.

One way of achieving this is to multiply their products by creating multiple variations of the same design, commonly referred to as assembly variants.

nVisage's built-in VCS interface and assembly variant support solves the multiple demands that team-based engineering development places on design capture tools.

The increasing complexity of designing electronics is leading engineers to seek out and use multiple and varied design solutions.

Device technologies such as FPGAs are beginning to have a major impact on design methodologies, and as device capacities increase and prices continue to fall, these components will find their way into an ever-increasing number of applications.

In this emerging design landscape of mixed physical and virtual componentry, it is becoming necessary for engineers to have access to tools that allow them to work efficiently in multiple design realms.

nVisage does this by fully supporting both schematic and VHDL design methodologies, and by providing a schematic environment that supports features such as nested multiple channels and raises the sophistication of the schematic capture process to the level where it efficiently supports complex digital designs.

Time-to-market pressures dictated by the commercial realities of today's electronics industry also mean that, while design complexity has increased, the time available for creation, testing and prototyping is decreasing.

This means efficient design verification must become an integral part of any design capture system.

nVisage supports the concept of "verify as you design" by incorporating relevant simulation technologies, such as Spice simulation, VHDL simulation and signal integrity analysis, into the design environment.

This allows engineers to validate their designs as part of the capture process, without the need to recreate design data in separate simulation environments.

Modern electronic devices make use of a variety of technologies and design techniques.

To capture these designs, engineers require a tool that supports multiple design entry methods, multiple methods of design verification and visualisation, and multiple means of design implementation.

nVisage allows the engineer to operate in the multiple dimensions needed to meet the challenges of modern design capture.

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